Chinese design
Who designs and controls the chip architecture and software?
Sovereignty is more than chip design
Useful domestic AI compute is advancing faster than full supply-chain independence.
Who designs and controls the chip architecture and software?
Where are the compute dies, memory, and packages manufactured?
Can production expand without foreign tools, components, materials, or replacement parts?
Reference: ASML / Nikon
Prototype and early tool deliveries do not establish reliable volume production.
Reuters · Initial domestic immersion DUV production (source)Reuters · China’s EUV prototype program (source)Reference: Zeiss / TRUMPF / Cymer
Projection optics, stable light sources, and precision integration remain difficult.
Financial Times · Huawei and the domestic lithography supply chain (source)SIOM / CAS · Laser and optics research (source)Reference: Applied Materials / Lam / TEL
Domestic suppliers cover substantial etch, deposition, cleaning and polishing work.
ACM Research · Semiconductor equipment portfolio (source)Hwatsing · CMP and related process equipment (source)NAURA · Process equipment portfolio (source)Reference: KLA / Hitachi High-Tech
Inspection sensitivity, overlay, and process control determine usable yield.
Skyverse · Inspection and metrology portfolio (source)Reference: Synopsys / Cadence / Siemens EDA
Replacing individual tools is easier than qualifying a complete frontier design flow.
Empyrean · EDA portfolio (source)Reference: TSMC
Domestic advanced logic works, but yield, capacity and process scaling constrain economics.
TechInsights · SMIC N+3 process analysis (source)TSMC · Foundry process portfolio (source)Reference: TSMC CoWoS / ASE / Amkor
Large compute dies and HBM must be integrated at production yield.
JCET research team · XDFOI packaging manufacturability research (source)Reference: SK hynix / Samsung / Micron
NAND is a relative strength; sufficient qualified HBM is the immediate compute constraint.
CXMT · DRAM portfolio (source)Reuters · HBM shortages raise Chinese accelerator prices (source)YMTC · NAND and enterprise storage portfolio (source)Reference: NVIDIA / AMD / Google TPU
Commercial alternatives are advancing faster than independently demonstrated frontier parity.
Huawei · Ascend hardware and software portfolio (source)SemiAnalysis · Continuous inference benchmark dashboard (source)MLCommons · MLPerf Training v6.0 submissions (source)Reference: NVLink / InfiniBand / Broadcom
Scale-up fabrics and Ethernet RDMA can compensate for some device limitations.
Huawei / SiliconFlow · Serving LLMs on Huawei CloudMatrix384 (source)H3C · Data-center networking portfolio (source)Reference: Coherent / Lumentum ecosystem
Chinese module suppliers compete globally, with continuing foreign-component dependencies.
Eoptolink / Broadcom · 1.6T transceivers using Broadcom DSPs (source)InnoLight · Optical networking portfolio (source)Reference: CUDA / cuDNN / NCCL
Kernel coverage, correctness, and recovery determine effective hardware performance.
Zheng Yu, CUHK Shenzhen · Independent Ascend deployment field study (source)Huawei · Ascend hardware and software portfolio (source)Moore Threads · GPU and MUSA portfolio (source)The Observatory’s forecasts, dated 2026-09-11. These are judgments with uncertainty, not reported milestones.
Now–2028
An existing global strength, with continued foreign-component dependencies.
Confidence: High
Eoptolink / Broadcom · 1.6T transceivers using Broadcom DSPs (source)InnoLight · Optical networking portfolio (source)2026–2029
Substantial domestic substitution and selective cost/performance wins on established workloads.
Confidence: High domestically; medium globally
2027–2030
More competitive aggregate capability, often with higher hardware and power requirements.
Confidence: Medium
Huawei / SiliconFlow · Serving LLMs on Huawei CloudMatrix384 (source)2027–2030
Useful domestic volume can improve before parity with the fastest contemporary memory.
Confidence: Medium
Late 2020s
Viable domestic training expands, while efficiency, software flexibility and reliability remain disadvantages.
Confidence: Medium
Into the 2030s
First successful chips can precede commercially competitive manufacturing by years.
Confidence: High on direction; low on dates